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| PDM41256 256K Static RAM 32K x 8-Bit Features s High-speed access times Com'l: 7, 8, 10, 12, and 15 ns Ind'l: 8, 10, 12, and 15 ns s Low power operation (typical) - PDM41256SA Active: 400 mW Standby: 150 mW - PDM41256LA Active: 350 mW Standby: 25 mW s Single +5V (10%) power supply s TTL-compatible inputs and outputs s Packages Plastic SOJ (300 mil) - TSO Plastic TSOP - T 1 2 3 4 5 6 7 8 9 10 11 12 Description The PDM41256 is a high-performance CMOS static RAM organized as 32,768 x 8 bits. This product is produced in Paradigm's proprietary CMOS technology which offers the designer the highest speed parts. Writing to this device is accomplished when the write enable (WE) and the chip enable (CE) inputs are both LOW. Reading is accomplished when WE remains HIGH and CE and OE are both LOW. The PDM41256 operates from a single +5V power supply and all the inputs and outputs are fully TTLcompatible. The PDM41256 comes in two versions, the standard power version PDM41256SA and a low power version the PDM41256LA. The two versions are functionally the same and only differ in their power consumption. The PDM41256 is available in a 28-pin plastic TSOP and a 28-pin 300-mil plastic SOJ. Functional Block Diagram Rev. 2.0 - 7/17/96 3-33 PDM41256 Pin Configurations TSOP SOJ Pin Description Name A14-A0 I/O7-I/O0 OE WE CE VCC VSS Description Address Inputs Data Inputs/Outputs Output Enable Input Write Enable Input Chip Enable Input Power (+5V) Ground Truth Table OE X L X H WE X H L H CE H L L L I/O Hi-Z DOUT DIN Hi-Z MODE Standby Read Write Output Disable NOTE: 1. H = VIH, L = VIL, X = DON'T CARE Absolute Maximum Ratings (1) Symbol VTERM TBIAS TSTG PT IOUT Rating Terminal Voltage with Respect to Vss Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Com'l. -0.5 to +7.0 -55 to +125 -55 to +125 1.0 50 Ind. -0.5 to +7.0 -65 to +135 -65 to +150 1.0 50 Unit V C C W mA NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RA TINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended DC Operating Conditions Symbol VCC VSS Commercial Industrial Parameter Supply Voltage Supply Voltage Ambient Temperature Ambient Temperature Min. 4.5 0 0 -40 Typ. 5.0 0 25 25 Max. 5.5 0 70 85 Unit V V C C 3-34 Rev. 2.0 - 7/17/96 PDM41256 DC Electrical Characteristics (VCC = 5.0V 10%) PSM41256SA Symbol ILI ILO VIL VIH VOL VOH Parameter Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL=8 mA, VCC = Min. IOL = 10 mA, VCC = Min. IOH = -4 mA, VCC = Min. Test Conditions VCC = MAX., VIN = Vss to VCC VCC= MAX., CE = VIH, VOUT = Vss to VCC Com'l/ Ind. Com'l/ Ind. Min. -5 -5 -0.5(1) 2.2 -- -- 2.4 Max. 5 5 0.8 6.0 0.4 0.5 -- PSM41256LA Min. -5 -5 -0.5(1) 2.2 -- -- 2.4 Max. 5 5 0.8 6.0 0.4 0.5 -- A A V V V V Unit 1 2 3 4 NOTE: 1. VIL(min) = -3.0V for pulse width less than 20 ns. Power Supply Characteristics -7 Symbol Parameter ICC Operating Current CE = VIL f = fMAX = 1/tRC VCC = Max IOUT = 0 mA ISB Standby Current CE = VIH f = fMAX = 1/tRC VCC = Max ISB1 Full Standby Current CE VCC - 0.2V f=0 VCC = Max VIN VCC - 0.2V or 0.2V -8 Ind. 210 190 -10 Com'l. 190 170 Ind. 200 180 -12 Com'l. 180 160 Ind. 190 170 -15 Com'l. 170 150 Ind. 180 160 Units mA mA Power Com'l. Com'l. SA LA 210 190 200 180 5 6 7 8 9 SA LA SA LA 90 90 20 5 80 80 20 5 80 80 20 10 70 70 20 5 70 70 20 10 60 60 20 5 60 60 20 10 50 50 20 5 50 50 20 10 mA mA mA mA SHADED AREA = PRELIMINARY DATA NOTE:All values are maximum guaranteed values. Capacitance(1) (TA = +25C, f = 1.0 MHz) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Max. 8 8 Unit pF pF 10 11 12 NOTE: 1. This parameter is determined by device characterization but is not production tested. Rev. 2.0 - 7/17/96 3-35 PDM41256 AC Test Conditions Input pulse levels Input rise and fall times Input timing reference levels Output reference levels Output load VSS to 3.0V 3 ns 1.5V 1.5V See Figures 1 and 2 Figure 1. Output Load Equivalent Figure 2. Output Load Equivalent (for tLZCE, tHZCE, tLZWE, tHZWE, tLZOE, tHZOE) Figure 3. 3-36 Rev. 2.0 - 7/17/96 PDM41256 Read Cycle No. 1(1) 1 2 3 Read Cycle No. 2(2) 4 5 6 7 AC Electrical Characteristics Description READ Cycle READ cycle time Address access time Chip enable access time Output hold from address change Chip enable to output in low Z(3, 4, 5) Z(3, 4, 5) Sym tRC tAA tACE tOH tLZCE tHZCE tPU tPD tAOE tLZOE tHZOE 0 5 0 7 5 0 6 3 5 5 0 8 5 0 6 --7(6) --8(6) -10(6) -12 -15 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 7 7 7 3 5 6 0 10 5 0 6 8 8 8 3 5 6 0 12 6 0 6 10 10 10 3 5 6 0 15 8 12 12 12 3 5 6 15 15 15 ns ns ns ns ns ns ns ns ns ns ns 8 9 10 11 12 3-37 Chip disable to output in high Chip enable to power up time(4) Chip disable to power down time(4) Output enable access time Output enable to output in low Z(4, 5) Output disable to output in high Z(4, 5) SHADED AREA = PRELIMINARY DATA. Notes referenced are after Data Retention Table. Rev. 2.0 - 7/17/96 PDM41256 Write Cycle No. 1 (Write Enable Controlled) Write Cycle No. 2 (Chip Enable Controlled) AC Electrical Characteristics Description WRITE Cycle WRITE cycle time Chip enable to end of write Address valid to end of write Address setup time Address hold from end of write Write pulse width Data setup time Data hold time Write disable to output in low Z Write enable to output in high (4, 5) -7(6) Sym tWC tCW tAW tAS tAH tWP tDS tDH tLZWE tHZWE Z(4, 5) -8(6) -10(6) -12 -15 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 7 7 7 0 0 7 6 0 0 3 8 8 8 0 0 8 7 0 0 3 10 10 10 0 0 10 7 0 0 3 12 10 10 0 0 10 7 0 0 3 15 12 12 0 0 11 7 0 0 3 ns ns ns ns ns ns ns ns ns ns SHADED AREA = PRELIMINARY DATA. 3-38 Rev. 2.0 - 7/17/96 PDM41256 Low VCC Data Retention Waveform 1 2 3 Data Retention Electrical Characteristics (LA Version Only) Symbol VDR ICCDR Parameter VCC for Retention Data Data Retention Current CE VCC - 0.2V VIN VCC - 0.2V or 0.2V VCC = 2V VCC = 3V Test Conditions Min. 2 -- -- 0 tRC Typ. -- 95 350 -- -- Max. -- 500 750 -- -- Unit V A A ns ns 4 5 6 7 8 9 10 11 12 tCDR tR(4) Chip Deselect to Data Retention Time Operation Recovery Time NOTES: (For three previous Electrical Characteristics tables) 1. The device is continuously selected. Chip Enable is held in its active state. 2. The address is valid prior to or coincident with the latest occuring Chip Enable. 3. At any given temperature and voltage condition, tHZCE is less than tLZCE. 4. This parameter is sampled. 5. The parameter is tested with CL = 5 pF as shown in Figure 2. Transition is measured 200 mV from steady state voltage 6. Vcc = 5V 5%. Rev. 2.0 - 7/17/96 3-39 PDM41256 Ordering Information 3-40 Rev. 2.0 - 7/17/96 |
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